AXI4 interfaces (full and AXI-Lite)

The AXI4 interface is a full-featured processor interface used by ARM to allow the easy connection of peripherals to their processors. Xilinx has adopted this interface to connect its hard and soft processors to other cores, whether AXI-Lite, full, or streaming. Because it is full-featured, it can be costly to implement and should only be considered when you need an addressable interface with high performance or bursting capability.

Hard IP refers to physical IP cores built into a Xilinx design. Examples of these would be PCIe interfaces, embedded ARM processors in a Xilinx Zynq FPGA, or hardened memory controllers. These are IP blocks that exist whether you use them or not.

Soft IP refers to IP that you create or Xilinx provides that is compiled in the FPGA fabric. It only exists in a design if you reference it.

There are five components to an AXI full or AXI-Lite interface. Read interfaces consist of an address component...