Understanding the LLVM target backend structure

After the LLVM IR is optimized, the selected LLVM target is used to generate the machine code from it. Among others, the following tasks are performed in the target backend:

1. The directed acyclic graph (DAG) used for instruction selection, usually referred to as the SelectionDAG, is constructed.
2. Machine instructions corresponding to the IR code are selected.
3. The selected machine instructions are ordered in an optimal sequence.
4. Virtual registers are replaced with machine registers.
5. Prologue and epilogue code is added to functions.
6. Basic blocks are ordered in an optimal sequence.
7. Target-specific passes are run.
8. Object code or assembly is emitted.

All these steps are implemented as machine function passes, derived from the MachineFunctionPass class. This is a subclass of the FunctionPass class, one of the base classes used by the old pass manager. As of LLVM 12, the conversion of machine function...