Chapter 4: Computer System Components
Exercise 1
Create a circuit implementation of a NAND gate using two CMOS transistor pairs. Unlike NPN transistor gate circuits, no resistors are required for this circuit.
Answer
The diagram for this circuit is as follows:
Figure 3: NAND gate circuit
Exercise 2
A 16-gigabit DRAM integrated circuit has two bank group selection inputs, two bank selection inputs, and 17 row address inputs. How many bits are in each row of a bank in this device?
Answer
The DRAM circuit contains 16 gigabits = 16 × 230 bits.
The number of address bits is 2 bank group bits + 2 bank bits + 17 row address bits = 21 bits.
The row dimension of each bank is therefore (16 × 230) ÷ 221 = 8,192 bits.
