Supporting new machine instructions
The CPU you are targeting may have machine instructions not yet supported by LLVM. For example, manufacturers using the MIPS architecture often add special instructions to the core MIPS instruction set. The specification of the RISC-V instruction set explicitly allows manufacturers to add new instructions. Or you are adding a completely new backend, and then you must add the instructions of the CPU. In the next section, we will add assembler support for a single, new machine instruction to an LLVM backend.
Adding a new instruction to the assembler and code generation
New machine instructions are usually tied to a certain CPU feature. Then the new instruction is only recognized if the user has selected the feature using the --mattr= option to llc.
As an example, we will add a new machine instruction to the MIPS backend. The imaginary, new machine instruction first squares the value of the two input registers $2 and $3 and assigns the sum...
