Project 5 – Keeping cars in line
A classic design challenge for budding engineers is designing a traffic light controller. The Xilinx project can be found in CH5/SystemVerilog/build/traffic_light/traffic_light.xpr or CH5/VHDL/build/traffic_light/traffic_light.xpr.
Figure 5.14: Traffic light controller intersection
The preceding diagram shows the basic scenario. We have an intersection with four traffic lights and four sensors labeled up, down, left, and right.
The ground rules are as follows:
- When a light is green, it will stay green for a minimum of 10 seconds.
- When a car goes through a green light, it is ignored.
- When a car waits at the red light, it signals the green to switch after it has been green for 10 seconds.
The light will stay yellow for 1 second when transitioning from green to red.
We’ve defined the problem. The first step, as always, is to create our state diagram.
