Recall that the interrupt controller chip (the PIC/GIC) will have a mask register. The OS can program it to mask or block hardware interrupts as required (of course, some interrupts may be unmaskable; the non-maskable interrupt (NMI) is a typical case that we discuss later in this chapter).Â
It's important to realize, though, that keeping interrupts enabled (unmasked) as much as possible is a critical measure of OS quality! Why? If an interrupt(s) is blocked, the peripheral cannot be responded to and the system's performance lags or suffers as a result (merely pressing and releasing a keyboard key results in two hardware interrupts). You must keep interrupts enabled for as long as possible. Locking with the spinlock will cause interrupts and preemption to be disabled! Keep the critical section short (we'll cover locking in depth in the last two chapters of this book).
Next, when...
